Trace Connolly Photography has added a photo to the pool:

Trace Connolly Photography has added a photo to the pool:

Trace Connolly Photography has added a photo to the pool:

Trace Connolly Photography has added a photo to the pool:

Trace Connolly Photography has added a photo to the pool:

Trace Connolly Photography has added a photo to the pool:

New alliance with the Netherlands and Baltic and Nordic countries comes in response to 41% increase in Russian naval activity around UK

Russian naval activity around the UK has increased by 41% in the first nine months of the year, a British defence minister has said, as the Royal Navy announced plans to step up a 10-country maritime defensive effort in response.

Luke Pollard, the minister for defence readiness, described the figure as “a huge increase”, justifying a new drone and warship initiative from “the alliance of beer-drinking nations” – the UK, the Netherlands and the Baltic and Nordic countries.

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• Imola stood down as back-up plan to finish the year

• Qatar and Abu Dhabi races set to go ahead as planned

Imola has been stood down as a back-up plan for the Formula One season finale as the sport pushes ahead with its scheduled Middle East races.

The Italian venue, 20 miles from Bologna, was lined up to replace Abu Dhabi as the final race amid concern over the ongoing conflict in the region.

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From Agatha Christie to a new generation of crime writers, cryptic crosswords have long held a place in murder-mystery fiction. Debut novelist and Guardian crossword setter Alys Cummings explains why the two make such natural companions

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A cryptic crossword and a murder mystery are each bound by an unspoken agreement between the creator and reader: I will give you enough information to solve this, but you must put the pieces together yourself.

So it’s no wonder that crime writers, from Agatha Christie to Dorothy L Sayers, and TV shows, from Inspector Morse to Inside No 9, have been drawn to the puzzles in their stories. The latest writer to enter the cruciverbalist crime arena is Alys Cummings, whose debut novel, Murder Most Cryptic, was published in October.

Upside-down cakes on the rack (8)

Record, EP and lyrics initially included in reissued album cover (8)

Here’s a tip: stick with your revised version (4,3,6)

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Jason Leon Watford said he ‘snapped’ after verbal dispute with the woman, before allegedly killing her in a cabin

A passenger of a Texas-based cruise ship has been charged with murdering a woman in their cabin on Sunday on the first day of their voyage.

Crew members aboard the MSC Seascape found the unidentified victim deceased and face down on the cabin floor, with Jason Leon Watford sitting in a corridor outside scrolling through his phone, according to an FBI affidavit that details the alleged crime.

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After teasing its 256-core Epycs for more than a year, AMD is finally ready to talk about architectural changes to the Zen core that not only make it possible, but will eventually power its next generation of Ryzen processors in desktop and mobile PCs. During a press event in Las Vegas last week, AMD spilled the beans on its latest Zen cores, which promise an average 27 percent uplift in instructions per clock (IPC) across a variety of AI and server workloads, along with boosted clocks ranging from 4.1 to 5.3 GHz. We expect to see even higher frequencies on consumer chips before long, but AMD isn’t quite ready to talk about Ryzen just yet. CPU performance is a function of power, IPC, and clocks, and with gains across all three, the cores are shaping up to be one of the company’s biggest generational jumps ever. A tale of two cores As in past Epyc launches, Zen 6 isn’t one core. It comes in two flavors: a frequency-optimized variant (Zen 6) and a density-optimized version (Zen 6c). This split dates back to the launch of AMD’s Bergamo Epycs in 2023, which packed 128 compact Zen 4c cores into just eight chiplets. The chip’s debut drew comparisons to Intel’s still relatively new Efficient (E-cores) for obvious reasons. But under the hood, AMD’s Zen 4c was nothing like what Intel was doing. The core itself was nearly identical to Zen 4; it simply traded clocks and a bit of cache per core for a more densely packed CPU die. The only difference between running an application on Bergamo or Genoa was how quickly it executed. The same could not be said of Intel’s P and E cores, which used different ISAs. This remained a defining characteristic and advantage of AMD’s compact core architecture through Zen 5, which allowed it to ship Turin parts with up to 192 cores without users having to worry about whether their app was running on a compact core or not. With Zen 6c, at least as we understand it, this philosophy is largely unchanged. Both Zen 6 and Zen 6c share the same ISA, with clock being the main differentiator. There are other micro-architectural differences between the two cores designed to balance IPC and clock speeds more effectively. Looking at the core’s block diagram, this isn’t immediately obvious. Zen 6 and Zen 5 share a very similar front and backend. We'd be tempted to call the core iterative if it weren't for the 20 to 31 percent IPC uplift for cloud and AI workloads that AMD claims over Zen 5. This suggests that core for core, a 4.1 GHz Zen 6c-based Venice Epyc should deliver performance on par with a Zen 5-based Turin Epyc running at 5 GHz. That's a pretty sizable jump, but just because AMD is seeing generational performance uplift in enterprise server and cloud workloads doesn't mean we'll see the same gains on the client side. Many will recall the roughly 5 percent performance gains gaming PC enthusiasts reported with the Ryzen 9000-series, leading to the rather unfortunate turn of phrase "Zen 5 percent." That happened because game engines at the time simply weren't CPU-bottlenecked, and so faster cores could only raise the ceiling so much. Even so, AMD fellow and "Zen daddy" Mike Clark tells El Reg that PC buyers expect more than a 6 percent gain from Zen 6. We're glossing over a bunch of low-level architectural optimizations here, but according to Clark, one of the biggest drivers of performance was to the front end. Zen 5 introduced a dual front end, which for simple workloads worked great, but lost a lot of steam when confronted with more dynamic loads. "The Zen 6 team did a really good job for those larger footprint workloads that have a bipolar nature," Clark said. "It's not something that comes through. You're not going to see it in a block diagram very well. It's sort of subtle... but it's a big lever." Another contributor was the move to a distributed scheduler in the out-of-order pipeline. One of the biggest performance drivers in modern CPU cores is that they don't execute instructions in the order they receive them. Instead, they reorder the instructions so as to keep the core's backend execution units fed with a constant stream of instructions. This is where we see the biggest difference between Zen 6 and Zen 6c. To account for the slower clocks on the latter core, AMD gave the core's scheduler deeper queues, which Clark tells us helps with higher-latency workloads. Meanwhile, from what we understand, Zen 6's shallower queue enables it to clock higher on less power. Finally, on the backend, AMD made several subtle changes which should have major implications for vector heavy workloads, including AI. One of the more significant was the ability to perform four AVX2 or two AVX-512 loads per cycle. While this doesn't improve AVX-512 performance much, for applications that haven't been updated to use it, the core is now able to perform twice as many loads, which should improve throughput for legacy applications. This should come in handy, particularly on PCs, where Intel's outright lack of AVX-512 support has made AVX2 the lowest common denominator for a lot of software. That's not to say AVX-512 didn't get some love this generation. For those running AI workloads on CPUs, Zen 6 now natively supports FP16 datatypes. Previously FP16 was supported, but required padding the data to FP32, which meant the lower precision didn't buy much in terms of performance. That's no longer the case in Zen 6. And while we're on the topic of AI acceleration, Clark notes that Zen 6 doubled the VNNI-INT8 pipes from two to four, and should effectively double throughput for workloads that support it. Feeding the beast While not strictly part of the core, AMD's Zen 6 processors also address one of the biggest asymmetries associated with its frequency and density optimized cores. Going back to Bergamo, opting for a density-optimized Epyc didn't just come at the expense of clocks, but cache too. Each Zen 4c or Zen 5c chiplet contained twice as many cores, but the same amount of L3 cache. With Zen 6 and Zen 6c, you may be giving up some clocks, but cache per core is now a constant 4 MB. As we discussed in a Venice deep dive back in September, each of the processor's eight CPU dies contain 12 or 32 cores and 48 and 128 MB respectively. The benefit here is that users don't have to worry about different ISAs or cache hierarchies when optimizing their software stacks against AMD's Epyc processors. The same cannot be said of Intel's Xeon processors. As we alluded to earlier, Chipzilla's performance and efficiency cores use different micro-architectures, ISAs, cache hierarchies, clocks, and even cluster their cores differently. This can pose real headaches if you have workloads that take advantage of fat vector registers like AVX-512, or accelerators like AMX, which will work just fine on Intel's P-cores but won't even run on their E-cores. This, along with support for SMT (Hyperthreading), which Intel has dropped for now, could help the House of Zen vacuum up even more market share from its long-time rival. ®

AMD's cache-packed Epyc X chips are officially making a comeback. Based on the House of Zen's frequency-optimized SKUs we looked at back in September, its HPC-optimized Venice-X parts will offer up to 96 cores and use the company's 3D V-Cache chip stack tech to triple the L3 cache density to more than a gigabyte. But before you get too excited about another cache-packed Epyc, it'll be a little while before they actually ship. AMD expects the Venice-X to begin trickling out in the second half of 2027. First teased at CES earlier this year, the chips are primarily aimed at latency-sensitive technical and scientific computing workloads like computational fluid dynamics and electronic design automation (EDA). AMD itself relies heavily on its X-series Epycs for EDA workloads like functional verification testing, which is used to simulate silicon in order to ensure it behaves as it's intended to. According to AMD Fellow Phil Steinke, by keeping more of the model in cache, the CPU cores don't have to wait as long for data to move in and out of system memory. Normally, boosting L3 capacity would have required larger chiplets with lower yields, but that's not how AMD has gone about it for the past four years. Instead, it used advanced packaging to give its existing CPU dies a little SRAM backpack. This tech has been around for several generations now, having first debuted in the Ryzen 7 5800X3D back in 2022. That consumer desktop chip stacked a 64 MB SRAM tile on top of an 8-core chiplet, boosting L3 capacity to 96 MB. The extra cache made the chip one of the most potent gaming CPUs of the time. Later that year, AMD brought the same technology to its Milan generation of Epycs as the company expanded its portfolio to address a wider range of workloads. The extra cache was popular enough to justify a second generation of X-series Epycs, which launched in 2023. But then, nothing. When AMD unveiled its 5th-gen Epycs in late 2024, there was no Turin-X on the roadmap. According to Madhu Rangarajan, who runs AMD's compute and enterprise AI products biz, this was intentional. "We are not doing the X every generation.... The enterprise HPC kind of market tends to have a cadence that's a little bit slower, so that's what drives our cadence." Venice-X marks the return of AMD's X-chips, and for the most part, the processor largely follows the same recipe as its predecessors. Each of the chip's up to eight CPU dies is now bonded to a 96 MB SRAM tile using advanced packaging, for a total of 144 MB of L3 per chiplet or 1,152 MB per socket, which you might have noticed is the same as in the Genoa-X parts they replace. But while core count and cache capacity haven't increased, clock speeds certainly have, with Venice now hitting 5.3 GHz compared to Genoa-X at just 3.7 GHz. "In Milan and Genoa, there was one trade-off. You either had to choose something that was high frequency or you chose something with 3D V-Cache." HPC likes both, Rangarajan told El Reg. The method for integrating the SRAM tile required this kind of compromise. Stacking SRAM on top of the compute chiplets boosted L3 caches, but also trapped heat, which limited boost clocks. So, for the Zen 5 generation, AMD moved the SRAM tile from the top of the stack to the bottom. With the SRAM tile no longer acting as a blanket, the chips could run hotter and faster for longer. But while gamers enjoyed the higher clocks and bigger caches on AMD's Ryzen 9000 processors, only now with Venice-X are those improvements making their way into Epyc. Because customers no longer have to choose between big caches and fast clocks, Rangarajan believes the chip may see wider adoption. "I think it's going to end up being much bigger in HPC than the previous generations where we had to make that tradeoff." Curiously, if frequency weren't such a high priority, Venice-X may not have needed 3D stacked SRAM in the first place. As we reported earlier this year, AMD's top-specced Venice CPUs boast 256 cores and 1,024 MB of L3 cache. AMD could have just fused off 160 of the cores and achieved a similar cache-per-core ratio. In fact, AMD did something like this for the Turin generation: For the Epyc 9175F, AMD essentially took a 128-core part and fused off 112 of the cores. What was left was a 16-core part with 512 MB of last-level cache. "You could do that [with Venice], but then you don't get the frequency part of it. The Fmax would be at 4.1 gigahertz and not 5.3 GHz," Rangarajan said. "Venice X really changes the game," he added. "For the first time, you can get the larger L3 in our highest frequency part." ®

AMD's upcoming Verano processors aren't like any Epyc CPUs we've seen before. Rather than general-purpose workloads, Verano is designed specifically to power AMD's next generation of GPU servers. In an interview with The Register during a press event in Las Vegas last week, Madhu Rangarajan, CVP of AMD's compute and enterprise AI products business, described Verano as being the first step towards building something that more closely resembles Nvidia's Vera Rubin superchips. "Verano is really designed for an integrated CPU+GPU rack scale solution," he said. "From that perspective, I wouldn't say the CPU is a competitor to Vera. In a head note, I'd say the Verano+GPU solution is a competitor to Vera+Rubin." For reference, Vera Rubin and the GB200 and GB300 that came before it aren't your typical server platforms. Instead they're more like an enormous single-board computer combining CPUs and GPUs into a tightly-integrated package. Each of Nvidia's superchips joins a single 88-core Vera CPU and 1.5 TB of LPDDR5X memory to a pair of Rubin GPUs via Nvidia's speedy NVLink-C2C interconnect. Rangarajan tells us Verano will be the host CPU for a similar class of product using AMD GPUs, and much like Nvidia's superchips, the CPU will also use notebook memory rather than conventional RDIMMS. However, unlike Vera, which is also being deployed as a standalone CPU in storage servers and agent sandboxes, Verano has a singular purpose: keeping its GPUs fed. (We assume they'll be MI500X GPUs.) This design choice reflects AMD's philosophy of one SKU per workload. As such, Verano's core count, clock speeds, memory bandwidth, power, and I/O have been rebalanced to keep its GPUs fed and not much else. Under the hood If we were to peel back Verano's heat spreader, the chip looks a lot like the Venice Epycs we looked at back in September. It features either six of AMD's core complex dies (CCDs) for a total of 72 high-frequency cores clocking to 5.3 GHz, or 192 density-optimized cores clocking to 4.1 GHz, depending on whether the customer's workloads prefer core density or faster clocks. But that's about where the visual similarities end. Much of the chip has been reworked to eliminate data flow bottlenecks between the CPU and the GPUs it is responsible for feeding. The chip features an entirely custom pair of I/O dies through which four LPDDR5X memory controllers are attached. Those memory controllers are currently being validated for use with 24 channels of memory at up to 8,533 MT/s. We're told that we may see that creep up a bit depending on how much headroom AMD has when the part starts shipping next year, but for now that's what AMD is validating against. That means the platform not only has fewer cores, but also slower memory. Peak theoretical memory bandwidth tops out at around 800 GB/s, which you might have noticed is half of what AMD's top-specced Venice parts can do and about 66 percent of Nvidia's Vera. What LPDDR seems to buy AMD is a 30 to 40 percent reduction in power consumption compared to RDIMMS, as well as a more compact footprint for liquid cooling. But it also comes with some downsides. In its first incarnation, Verano won't be socketed. Instead it'll use a ball-grid array (BGA) that's soldered to the board, which will make it harder to service. "LPDDR tends to be quite finicky in terms of speeds. Every time you go through a connector, you tend to lose a pin or two, and you already have one connector with the SoCam itself. So to minimize any of those losses in speed, we went BGA on the CPU," Rangarajan told us. Unlike with a lot of notebooks, the memory itself won't be soldered down and will use the same SOCAMM2 modules found in Nvidia's Vera-Rubin and Vera-Vera CPU Superchips. Even so, Verano looks like a bit of a downgrade compared to Venice except when it comes to CPU-to-GPU connectivity. Fatter pipes Historically, AMD's CPU-to-GPU communication has been done over PCIe. It works but has usually required PCIe switches to keep up with all the GPUs, NICs, and storage on board. Nvidia's superchip dispensed with this, replacing PCIe with its NVLink-C2C interconnect, which provides 900 GB/s of bidirectional bandwidth to each of the system's GPUs. Venice and Verano do something similar. Unlike past Instinct accelerators, AMD's latest generation of GPUs aren't limited to PCIe for CPU-to-GPU communication. Instead, starting with Venice, AMD transitioned to using xGMI. Global memory interconnect (GMI) is how AMD has moved data between chiplets on its CPUs, GPUs, and APUs for several generations now. xGMI extends this to GPU-to-GPU and CPU-to-GPU communications. With Venice, xGMI link bandwidth tops out at 64 Gbps per lane, which the keen-eyed among you have probably already figured out is the same as PCIe 6.0. Verano takes this to another level. As we mentioned earlier, Verano disaggregated the memory controllers, and AMD appears to have reclaimed that space for fatter serializer deserializers (SerDes). Instead of 64 Gbps per lane, Verano's xGMI links top out at 112 Gbps, effectively giving it near PCIe 7.0 levels of bandwidth years before the spec ships in production CPUs. Rangarajan explains this is driven by what AMD's GPUs need to run optimally. AMD hasn't disclosed the ratio of CPUs to GPUs it's aiming for with Verano, so it's difficult to say how it compares to Nvidia. In a 2:1 ratio of GPUs to CPUs like we saw in Vera Rubin, Verano would deliver identical chip-to-chip bandwidth, while in a 1:4 ratio like we see in AMD's Helios racks, we'd be looking at about half the bandwidth at 448 GB/s. It's also not clear whether AMD has increased the number of xGMI links per I/O die for Verano or not, so bandwidth per GPU could be even higher. We expect more info closer to the MI500X's debut next year. Part of a broader ecosystem AMD doesn't expect Verano to replace Venice in every AI rack: The chip is designed specifically for use with Instinct accelerators. Moreover, AMD isn't waiting for Verano to roll out its Helios rackscale systems. As we discussed during Advancing AI earlier this year, those systems will feature 18 96-core Venice CPUs paired to 72 Instinct MI455X GPUs. Moving forward, AMD expects its Venice to remain a popular host processor for AI head nodes not just for its own GPUs but for the growing number of homegrown accelerators built by the great model houses. ®

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Soort Sinterklaas maar dan andersom. Met 180 km/u in 2,5 seconden uit een 350 meter hoge schoorsteen gejankt. Dat kost u dan: 4.2G en als je niet out gaat lukt het je om precies op het gewichtsloze moment te high-fiven en daarna op tijd aan je parachutekoord te trekken. En we willen op zich niks verklappen, maar dat lukt.

Bouw van de grootste menselijke katapult ooit

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Ook echt waanzinnig

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Moscow police have been ramping up the pressure on teenagers in Kitai-Gorod — a popular hangout spot — for months.

AMSTERDAM (ANP) - De AEX-index op de Amsterdamse beurs is dinsdag met kleine winst gesloten, mede geholpen door de chipbedrijven die verder stegen na de recente uitverkoop in de AI-sector. De aandacht van beleggers bleef uitgaan naar de affaire van topman Jensen Huang van AI-chipconcern Nvidia met een vermeende Chinese spion. Daarnaast kwam AI-bedrijf Anthropic met details over zijn beursgang en werden cijfers gemeld over de Amerikaanse inflatie.

ASML, ASMI en Besi gingen tot 2,6 procent vooruit, waarmee werd voortgeborduurd op de stijgingen van maandag. Zij profiteerden van de stevige plussen in de chipsector in New York van maandag. Nvidia ging echter wel omlaag door alle onrust rond de affaire van Huang, die nu wordt onderzocht door de FBI. Ook zijn aandeelhouders een rechtszaak begonnen tegen Nvidia en Huang vanwege misleiding.

De AEX eindigde 0,2 procent hoger op 1132,44 punten. Op maandag won de hoofdindex 0,8 procent. De MidKap klom 0,4 procent tot 1123,96 punten, na de plus van 1,2 procent op maandag.

Anthropic

Op de beurzen in Parijs en Frankfurt werden winsten behaald tot 0,6 procent. Londen sloot 0,3 procent lager.

Anthropic, het bedrijf achter chatbot Claude, kondigde aan dat de introductieprijs van zijn aandelen tussen de 70 en 78 dollar per stuk ligt. Met de beursgang, die mogelijk volgende week plaatsvindt, verwacht het bedrijf tot ruim 64 miljard dollar op te halen. De totale marktwaarde zou bij de beursgang, een van de grootste ooit, rond de 1,4 biljoen dollar liggen.

Amerikaanse inflatie

De Amerikaanse inflatie viel in oktober iets hoger uit dan verwacht, waardoor de kans op een renteverhoging door de Federal Reserve in december groter is geworden. In september kwam de Fed nog met de eerste renteverhoging in ruim drie jaar om de hoge inflatie tegen te gaan.

Shell stond opnieuw bij de dalers in de AEX met een min van 2 procent. Het olie- en gasconcern werd door de Spaanse bank Santander van de kooplijst gehaald. Daarnaast gingen de olieprijzen verder omlaag.

Bij de kleinere fondsen op Beursplein 5 dook de producent van elektromagnetische componenten Kendrion 10 procent in het rood na bekendmaking van kwartaalcijfers.

Felle kleuren en spaarpotjes op de website, de „cruciale systemen” van ABN Amro op de achtergrond: neobank Buut richt zich expliciet op jongeren. „Financieel opvoeden is lastig. Laten we eerlijk zijn.”

De rechterbuis van de Drechttunnel (A16) richting Rotterdam is dinsdag in de avondspits afgesloten. Dat komt door een kapotte vrachtwagen die olie achterliet op het wegdek. De vertraging liep rond 17:50 uur op tot ongeveer een uur.