COMPUTEX 2026 Intel’s Clearwater Forest Xeons were originally designed to power telco networks, SaaS apps, and other high-volume web-scale workloads. But by a stroke of luck, the x86 giant may have also built an agentic AI beast. AI model training, inference, and the GPUs that power them have dominated the discourse for the past few years, but with the rise of agentic harnesses like OpenClaw, CPUs are back in the limelight. In completing a task, these harnesses can make dozens or even hundreds of requests to gather information from the web, run and debug code, query databases, and interact with API services. All of those requests are run on CPU cores – and Intel’s Xeon 6+ processors happen to have 288 of them. That’s 200 more cores per socket than Nvidia’s new Vera CPUs, and more than twice as many as Arm’s recently unveiled AGI CPU, both of which are aimed squarely at agentic AI. Intel was able to achieve this density using a combination of advanced packaging, leading-edge 2 nm-class process tech, and a stripped-down processor core that it’s been refining for the better part of five years. Peel back Clearwater’s lid and you’ll find layer upon layer of silicon. Similar to AMD’s Epycs, Intel’s latest Xeon spreads its cores out across twelve 24-core tiles fabbed on its 18A process node. These tiles are stacked atop three tiles built on Intel 3, which contain the chip’s memory controllers and L3 cache. Meanwhile, PCIe and CXL connectivity and a host of dedicated accelerators are housed in a pair of I/O dies borrowed from Intel’s earlier Xeon 6900P-series parts. The shared I/O dies and common socket mean that Clearwater won’t require OEMs to ramp an entirely new platform. The chip can drop into existing board designs, easing adoption. A core compromise Clearwater may offer superior core density compared to the competition, but the cores themselves involve some compromises. The chip’s Darkmont E-cores don’t clock as high as Intel’s Xeon 6 P-cores, and lack AVX-512, AMX acceleration, and hyperthreading found in those cores. However, the new cores are by no means weak. Compared to Intel’s first round of E-core Xeons, which landed at Computex two years ago, Clearwater’s cores offer 17 percent higher instructions per clock on top of faster boost clocks. While certainly less capable than Intel’s P-core Xeons, the vast majority of agentic workloads probably won't miss these features. You certainly don’t need AVX-512 to run curl or a Python interpreter, or to execute a SQL query. This is probably why Arm opted to forgo wide vector registers on its AGI CPU as well. By and large, the code and jobs these agentic harnesses are running don’t need them, and they just end up eating up die area that could go toward larger caches or denser core clusters. But these workloads may benefit from the cornucopia of dedicated accelerators. Baked into the chip’s I/O dies are 16 accelerators designed to speed up everything from cryptographic operations and data movement to compression, decompression, and load balancing. Xeon 6+ will be offered in SKUs ranging from 144 to 288 cores with TDPs ranging from 330 to 450 watts. And thanks to new functionality baked into the chip, those deploying the parts will actually be able to see what processes are driving up power consumption. The broad range of core counts offers a couple of advantages, including flexibility for things like bandwidth per core. Adding more cores reaches a point of diminishing returns if you can’t keep them fed with data. Clearwater supports up to 12 channels of DDR5 memory at up to 8000 MT/s, no MRDIMM required, which works out to about 750 GB/s per socket, or between 2.5 GB/s and 5 GB/s per core depending on the SKU. That’s not as fast as Arm’s AGI CPU or Nvidia’s Vera, but not every workload is going to be memory-bound either. Where Clearwater fits in Intel’s lineup Chipzilla is positioning Clearwater for agentic deployments where density is more important than latency. We imagine the processor will be popular for powering chatbot features like web search or file conversion, where users won’t notice the extra second or two it takes to process. For latency sensitive workloads, Intel is peddling its P-core Xeons like Granite Rapids and its upcoming Diamond Rapids parts. The latter will boast up to 192 cores, 16 channels of DDR5, and support for PCIe 6.0. While Clearwater is well suited to running agentic workloads, the company is still marketing the chip old-school toward telcos and service providers as well. In the case of the latter, Intel hopes to capitalize on those looking to retire their aging Xeon fleets. The company claims a single Clearwater Forest system can replace as many as nine second-gen Xeon Scalable boxes. That sales point looks awfully compelling except for the fact that memory prices have more than tripled since this time last year, and service providers may be better off sweating their hardware for a little longer than paying a premium for DDR5. The big red AI-crazed elephant in the room While Intel may have the core count advantage for now, expect that to narrow considerably in just over a month. AMD is widely expected to launch its 256-core Venice Epycs during Advancing AI in San Francisco in July. The chip not only introduces refreshed cores, but also an entirely new package. From the brief glimpse we got at CES, AMD appears to have made the jump from eight or 16-core compute dies to using up to eight 32-core ones. We strongly suspect the 256-core part will use a “compact” or “dense” version of AMD's Zen 6 core architecture. The approach trades clocks for reduced die area, and it's what allowed AMD to pack 192 cores into its Turin Epycs when they launched in 2024. One key nuance to AMD’s approach is that the microarchitecture used by its compact cores is identical to that of its larger, frequency-optimized counterparts. The only thing that does change is the ratio of cache per core. That means customers don’t lose any features like AVX-512 when opting for a higher core count part. For agentic workloads, the winner between AMD's next-gen Epycs and Intel's Clearwater will probably come down to cost and power.®
